drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

749

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

239

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

467

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3222

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2096

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3767

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2832

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1349

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1349

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1345

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1154

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2508

#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L