drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

223

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

445

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3199

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2073

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3744

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2803

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1320

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1320

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1316

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1125

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2479

#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10