drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

242

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

470

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3225

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2099

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3770

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2835

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1352

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1352

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1348

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1157

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2511

#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L