drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

478

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3233

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2107

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3778

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2843

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1360

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1360

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1356

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1165

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2519

#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L