drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

241

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

469

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3224

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2098

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3769

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2834

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1351

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1351

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1347

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1156

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2510

#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L