drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3234

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2108

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3779

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2844

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

1361

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

1361

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

1357

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

1166

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

2520

#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L