drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

798

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

252

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

543

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3301

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2175

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3846

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2923

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2845

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2845

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2877

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2378

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3848

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6