drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

797

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

261

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

553

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3312

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2186

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3857

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2943

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2871

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2871

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2903

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2404

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3875

#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L