drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

786

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

780

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

246

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

537

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3295

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2169

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3840

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2917

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2839

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2839

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2871

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2372

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3842

#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0