drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

785

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

779

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

255

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

547

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3306

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2180

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3851

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2937

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2865

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2865

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2897

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2398

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3869

#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L