drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

789

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

783

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

257

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

549

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3308

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2182

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3853

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2939

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2867

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2867

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2899

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2400

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3871

#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L