drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

787

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

781

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

256

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

548

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3307

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2181

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3852

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2938

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2866

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2866

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2898

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2399

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3870

#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L