drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

546

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3304

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2178

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3849

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2926

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2848

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2848

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2880

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2381

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3851

#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9