drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

793

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

787

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

259

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

551

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3310

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2184

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3855

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2941

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2869

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2869

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2901

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2402

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3873

#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L