drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

791

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

785

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

258

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

550

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3309

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2183

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3854

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2940

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2868

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2868

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2900

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2401

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3872

#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L