drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

795

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

260

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

552

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3311

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2185

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3856

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2942

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2870

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2870

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2902

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2403

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3874

#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L