drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

262

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

554

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3313

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2187

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3858

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2944

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2872

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2872

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2904

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2405

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3876

#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L