drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3316

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2190

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3861

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2947

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

2875

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

2875

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

2907

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2408

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

3879

#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L