drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

626

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

691

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

632

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

694

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

696

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

752

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1279

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2903

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1735

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3371

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2424

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

3612

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

3643

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

3564

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

3164

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

4642

#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1