drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

3583

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2523

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

4345

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3452

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

3358

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

3382

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

3314

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

2909

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

4387

#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L