drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

737

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

584

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

743

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

927

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

915

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

36

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

80

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1517

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1520

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2958

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2054

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6347

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7151

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6174

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5351

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

800

#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L