drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

930

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

918

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

28

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

74

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1511

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1514

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2952

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2048

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6341

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7145

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6168

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5345

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

794

#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2