drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

929

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

917

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

37

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

81

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1518

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1521

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2959

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2055

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6348

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7152

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6175

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5352

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

801

#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L