drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

939

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

927

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

42

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

83

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1520

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1523

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2961

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2057

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6350

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7154

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6177

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5354

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

803

#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L