drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

58

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1493

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1496

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2934

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2024

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6317

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7121

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6144

#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10