drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

57

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1492

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1495

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2933

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2023

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6316

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7120

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6143

#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe