drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

50

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1485

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1488

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2926

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2016

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6309

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7113

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6136

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0