drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

61

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1497

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1500

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2938

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2031

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6324

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7128

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6151

#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L