drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

52

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1487

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1490

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2928

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2018

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6311

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7115

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6138

#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4