drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

59

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1494

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1497

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2935

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2025

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6318

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7122

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6145

#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12