drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

54

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1489

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1492

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2930

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2020

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6313

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7117

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6140

#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8