drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

35

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1468

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1471

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2909

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1993

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6287

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7090

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6113

#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10