drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

34

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1467

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1470

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2908

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1992

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6286

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7089

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6112

#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe