drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

27

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1460

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1463

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2901

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1985

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6279

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7082

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6105

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0