drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

38

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1472

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1475

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2913

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2000

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6294

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7097

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6120

#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L