drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

29

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1462

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1465

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2903

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1987

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6281

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7084

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6107

#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4