drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

36

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1469

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1472

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2910

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1994

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6288

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7091

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6114

#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12