drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

31

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1464

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1467

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2905

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1989

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6283

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7086

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6109

#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8