drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

502

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

519

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x00000018

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

506

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

538

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

540

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

620

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1127

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2633

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2868

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2860

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3941

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4191

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4234

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4058

#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18