drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

500

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

517

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

504

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

536

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

538

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

619

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1126

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2632

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2867

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2859

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3940

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4190

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4233

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4057

#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12