drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

498

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

515

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0x0000000c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

502

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

534

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

536

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

618

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1125

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2631

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2866

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2858

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3939

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4189

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4232

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4056

#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc