drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

488

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

505

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

492

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

524

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

526

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

609

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1116

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2622

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2857

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2849

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3930

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4180

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4223

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4047

#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0