drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

484

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

501

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

488

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

520

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

522

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

601

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1108

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2614

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2849

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2841

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3922

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4172

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4215

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4039

#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12