drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

486

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

503

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

490

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

522

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

524

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

602

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1109

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2615

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2850

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2842

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3923

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4173

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4216

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4040

#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18