drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

482

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

499

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

486

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

518

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

520

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

600

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1107

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2613

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2848

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2840

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3921

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4171

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4214

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4038

#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc