drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

480

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

497

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

484

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

516

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

518

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

599

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1106

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2612

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2847

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2839

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3920

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4170

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4213

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4037

#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6