drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

468

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

487

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x00000003

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

472

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

504

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

506

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1102

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2595

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2830

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2821

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3901

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4151

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4190

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4018

#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3