drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

467

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

486

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

471

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

503

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

505

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1103

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2601

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2836

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2828

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

3909

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4159

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4200

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4026

#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L