drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

348

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

347

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x00000008

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

352

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

384

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

386

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

506

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1028

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2397

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

3348

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

937

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4660

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4813

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4856

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4656

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

4228

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

5732

#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8