drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

319

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

308

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

319

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

351

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

353

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

2077

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

3315

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

904

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4627

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

4780

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4823

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

4623

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

4195

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

5699

#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L